DocumentCode :
3194125
Title :
Electrical modeling and simulation issues in ULSI packaging
Author :
Prince, J.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear :
1992
fDate :
18-25 June 1992
Abstract :
Summary form only given. Modeling and simulation capabilities are key components ULSI design systems yet to be developed. Issues in this area revolve around the critical ability to perform efficient simulation, i.e., the simulation with the least real-time delay before acceptably accurate results are available to the design engineer in an information format. Implicit in this is the premise that there is never enough computational and information management capability to fully analyze (no approximations or truncations) real designs in times consistent with human design engineering practice. The exploration and definition of the boundaries between different electrical analysis domains were discussed. Design data manipulation and information management, which are critical for systems involving a few dozen chips with a few thousand I/Os and a few tens of thousands of interconnect lines and which will become more of an issue when the chip I/O count and interconnect line count increase by one or two orders of magnitude, were also considered.<>
Keywords :
VLSI; packaging; semiconductor process modelling; ULSI packaging; electrical modelling; simulation; Computational modeling; Data engineering; Delay effects; Design engineering; Electronics packaging; Engineering management; Humans; Information management; Signal processing; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Antennas and Propagation Society International Symposium, 1992. AP-S. 1992 Digest. Held in Conjuction with: URSI Radio Science Meeting and Nuclear EMP Meeting., IEEE
Conference_Location :
Chicago, IL, USA
Print_ISBN :
0-7803-0730-5
Type :
conf
DOI :
10.1109/APS.1992.221660
Filename :
221660
Link To Document :
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