• DocumentCode
    3194769
  • Title

    Integration of a 3 level Cu-SiO/sub 2/ air gap interconnect for sub 0.1 micron CMOS technologies

  • Author

    Arnal, Vincent ; Torres, Joaquin ; Gayet, Philippe ; Gonella, Roberto ; Spinelli, Philippe ; Guillermet, Marc ; Reynard, Jean-Philippe ; Vérove, Christophe

  • Author_Institution
    STMicroelectron., Crolles, France
  • fYear
    2001
  • fDate
    6-6 June 2001
  • Firstpage
    298
  • Lastpage
    300
  • Abstract
    Integration of three level of SiO 2 air gap has been successfully achieved in a complete CMOS copper interconnect scheme. SiO 2 air gap is demonstrated to be a reliable ultra low k for sub 0.1 μm technologies with a well controlled dielectric constant below 2.
  • Keywords
    CMOS integrated circuits; air gaps; copper; integrated circuit interconnections; permittivity; silicon compounds; 0.1 micron; CMOS technology; Cu-SiO/sub 2/; copper interconnect; dielectric constant; process integration; three-level SiO/sub 2/ air gap; ultra-low-k dielectric; CMOS technology; Copper; Delay; Dielectric constant; Dielectric materials; Etching; Geometry; Parasitic capacitance; Permittivity; Ultra large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International
  • Conference_Location
    Burlingame, CA, USA
  • Print_ISBN
    0-7803-6678-6
  • Type

    conf

  • DOI
    10.1109/IITC.2001.930089
  • Filename
    930089
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3194769