• DocumentCode
    3195219
  • Title

    High speed parallel-prefix modulo 2n+1 adders for diminished-one operands

  • Author

    Vergos, H.T. ; Efstathiou, C. ; Nikolos, D.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Patras Univ., Greece
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    211
  • Lastpage
    217
  • Abstract
    We present a new methodology for designing modulo 2n+1 adders with operands in the diminished-one number system. The proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate; that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2n and modulo 2n-1 adders
  • Keywords
    VLSI; adders; digital arithmetic; integrated circuit design; logic design; VLSI implementations; analytical model; diminished-one number system; diminished-one operands; high speed parallel-prefix modulo 2n+1 adder design; standard-cell technology; Adders; Analytical models; Circuits; Concurrent computing; Design methodology; Digital arithmetic; Digital signal processing; Informatics; Signal processing algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on
  • Conference_Location
    Vail, CO
  • ISSN
    1063-6889
  • Print_ISBN
    0-7695-1150-3
  • Type

    conf

  • DOI
    10.1109/ARITH.2001.930121
  • Filename
    930121
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3195219