Driver design for DDR4 memory subsystems

As DDR4 continues to move from the design phase towards implementation, several challenges have been identified to successfully implement this high performance memory architecture for next generation systems. This paper investigates driver design selection for DDR4 systems. The paper studies the pros and cons of three driver design types namely: standard, pre-emphasis, and de-emphasis on typical net topogies of 1DPC (DIMM per channel) and 2DPC operated at 2400MT/s. For each driver type the impact of source termination on performance and power saving capability is discussed. Since the effects associated with different driver designs can be best understood in the time domain this paper uses behavioral models created in the SPICE format for simulations.