DocumentCode
3196014
Title
High speed DDR interface timing closure
Author
Soman, Sreekanth ; Brahme, Amit ; Patil, Mahendrasing
Author_Institution
Texas Instrum. (India) Pvt. Ltd., Bangalore, India
fYear
2010
fDate
25-27 Oct. 2010
Firstpage
289
Lastpage
292
Abstract
This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.
Keywords
DRAM chips; DDR controller; I/O buffer; high speed DDR interface timing closure; Crosstalk; Jitter; Noise; SPICE; Strontium; Switches; Timing; DDR3; SI; SSN; crosstalk;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-6865-2
Electronic_ISBN
978-1-4244-6866-9
Type
conf
DOI
10.1109/EPEPS.2010.5642791
Filename
5642791
Link To Document