Thermal-aware reliability analysis of nanometer designs

Increasing current densities in deep sub-micron designs necessitate accurate power and thermal analysis to help verify compliance with chip-level reliability specifications. This paper presents a thermal-aware analysis flow that accurately captures the effects of design topology, currents, and switching constraints. This static analysis flow demonstrates the need to compute temperature at the level of interconnect metal, via resistors and device fingers, and was used to verify reliability constraints on successive iterations of nanometer-level designs.