DocumentCode
319609
Title
A single-chip FPGA implementation of a self-synchronous cipher
Author
Millan, William ; Wong, Kim ; Wark, Melanie ; Dawson, Ed
Author_Institution
Inf. Security Res. Centre, Queensland Univ. of Technol., Brisbane, Qld., Australia
Volume
1
fYear
1997
fDate
4-4 Dec. 1997
Firstpage
223
Abstract
A new self-synchronous stream cipher has been implemented in a single Xilinx 4000 series FPGA chip, achieving a throughput of 60 Mbps. The cipher provides automatic resynchronisation after a bit-slip error, and offers more security than previous proposals of its type. We discuss cryptographic aspects of the cipher´s design, comment on its flexibility, and give details of the FPGA chip resource usage.
Keywords
cryptography; field programmable gate arrays; 60 Mbit/s; Xilinx 4000 series FPGA chip; automatic resynchronisation; bit-slip error; cryptography; security; self-synchronous stream cipher; single-chip FPGA; throughput; Australia; Communication channels; Cryptography; Data security; Feedback; Field programmable gate arrays; Information security; Proposals; Speech; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications., Proceedings of IEEE
Conference_Location
Brisbane, Qld., Australia
Print_ISBN
0-7803-4365-4
Type
conf
DOI
10.1109/TENCON.1997.647298
Filename
647298
Link To Document