High-throughput LDPC decoding architecture

A high-throughput decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) codes is developed in this paper. Regular pipelined schemes of the partially parallel decoder, which are adaptable to various decoding requirements, are derived to simplify the design and implementation. Utilizing normalized uniformly most powerful (UMP) belief propagation (BP) algorithm, pipelined partially parallel decoders for (7493, 3048), (7493, 4572) and (7493, 6096) LDPC codes are implemented on FPGA. Synthesis results show that, with 30 decoding iterations, the decoders for these codes archive throughputs of 108, 172 and 237 Mbps at the maximum operating frequencies of 151, 158 and 163 MHz respectively. The proposed architecture increases decoding throughput by more than four times compared with that of the traditional decoder.