Chip-package-board co-design for complex system-on-chip (SoC)

Device scaling has allowed us to pack more functionality in a smaller die area. The ever increasing number of interfaces and the complexity of advanced SoCs force custom package design for almost every device rather than using a standard of the shelf package. The time-to-market window is shrinking with rapidly growing demand in the consumer market. To meet package performance with reduced package size and cost constraints, early evaluation of package and board routing is required. Floorplan of today´s complex SoCs´ is driven not only by the package but also board and overall system design. Chip-Package-Board co-design is obligatory to meet performance and schedule requirements as well as to reduce the system cost. This paper talks about the co-design challenges on a 40nm complex SoC implementation.