DocumentCode
319610
Title
Pipelined architectures for the Viterbi algorithm
Author
Bóo, M. ; Brugera, J.D.
Author_Institution
Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
Volume
1
fYear
1997
fDate
4-4 Dec. 1997
Firstpage
239
Abstract
The main part of the Viterbi algorithm is a nonlinear feedback loop which presents a bottleneck for high-speed implementations. We propose four different solutions for increasing the computation speed of the Viterbi algorithm, three of them are based on the utilization of pipelined systems combined with efficient scheduling methodologies and the other one is based on the simplification of the ACS recursion to cut down the critical path of the system.
Keywords
Viterbi decoding; computational complexity; digital signal processing chips; pipeline arithmetic; ACS recursion; Viterbi algorithm; computation speed; image processing; memoryless source encoding; nonlinear feedback loop; pipelined architectures; scheduling; trellis coded quantization; Computer architecture; Contracts; Decoding; Equations; Feedback loop; Hardware; Image coding; Processor scheduling; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications., Proceedings of IEEE
Conference_Location
Brisbane, Qld., Australia
Print_ISBN
0-7803-4365-4
Type
conf
DOI
10.1109/TENCON.1997.647302
Filename
647302
Link To Document