High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4times4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18 mum CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1 k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.