Packaging challenges associated with warpage of ultra-thin chips

Ultra-thin chip warpage is believed to have significant impact on electrical behavior of devices and circuits when the chips are glue attached to a flexible substrate. In this paper, we have investigated this packaging related issue by comparing ultra-thin silicon chips of similar thickness (~20 μm) obtained from two fundamentally different fabrication technologies. We show that in spite of considerable structural and process-related differences, both type of chips exhibit the same degree of warpage. The electrical device characteristics on both chip type are almost identical. We also show that the degree and shape of warpage depends primarily on the chip layout and surface topology.