Title :
The least complex parallel Massey-Omura multiplier and its LCA and VLSI designs
Author :
Shayan, Yousef R. ; Le-Ngoc, Tho
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
After reviewing the Massey-Omura multiplier, as an illustrative example it is shown that there are three polynomials which generate GF(2/sup 5/) in normal basis representation. The three multipliers based on these polynomials are considered and the polynomial which results in the least complex multiplier design is found. Then, based on this polynomial and the resultant design, LCA and VLSI implementation of the GF(2s/sup 5/) multiplier is considered and compared.<>
Keywords :
VLSI; logic arrays; multiplying circuits; GF(2/sup 5/); Massey-Omura multiplier; VLSI implementation; least complex parallel multiplier; logic cell array implementation; polynomials; Decoding; Propagation delay; Reed-Solomon codes; Very large scale integration;
Conference_Titel :
Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC, Canada
DOI :
10.1109/PACRIM.1989.48388
