DocumentCode
3197408
Title
Design guidelines for low-ripple paralleled converter system
Author
Kohama, Teruhiko ; Tsunesada, Ryota
Author_Institution
Dept. of Electr. Eng., Fukuoka Univ., Fukuoka, Japan
fYear
2009
fDate
2-5 Nov. 2009
Firstpage
1131
Lastpage
1136
Abstract
Design guidelines for low-ripple paralleled converter system are proposed. Current and voltage ripples in output capacitor of paralleled converter system depend on duty ratio and number of converter modules. The ripples are estimated through a simplified circuit model which is available for any paralleled converter system. Optimum design example for paralleled system with low voltage-ripple is described to make proposed guidelines clear.
Keywords
power convertors; circuit model; current ripples; design guidelines; duty ratio; low-ripple paralleled converter system; output capacitor; voltage ripples; Automatic control; Capacitors; Circuits; DC-DC power converters; Delay estimation; Guidelines; Inductance; Interleaved codes; Low voltage; Pulse width modulation; design guidelines; interleaving operation; paralleled converter; zero ripple;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics and Drive Systems, 2009. PEDS 2009. International Conference on
Conference_Location
Taipei
Print_ISBN
978-1-4244-4166-2
Electronic_ISBN
978-1-4244-4167-9
Type
conf
DOI
10.1109/PEDS.2009.5385910
Filename
5385910
Link To Document