Eutectic wafer bonding for 3-D integration

Successful commercialization of MEMS products extremely depends on cost factors. Especially the role of integration technologies like packaging at different levels, combining MEMS with integrated circuits, and to realize 3-dimensional packaged devices is more important than ever. Bonding technologies at wafer level are key factors for 3-d integration, realizing the mechanical bond and fulfilling certain requirements like strength, hermeticity, and reliability as well as the electrical interconnection of the different functional components. From a great variety of bonding techniques eutectic bonding has got a special importance today because both hermetically sealed packages and electrical interconnects could be performed within one bonding process. Furthermore, there are some advantages such as low processing temperature, low resulting stress, and high bonding strength. These properties are mainly investigated up today. Since the early 90-ies eutectic wafer bonding is known from very large scale integration (VLSI) and is used very often in industry. Even before that time eutectic bond processes were already used in the field of chip bonding. Within this paper the development and investigation of at least two eutectic bonding technologies will be described and characterized. Although the mechanical and micro structural properties of the bond will be shown, the realization and test of electrical interconnects is focused very clearly. With an integration of certain test structures the bonding strength, the electrical properties, and the hermeticity of eutectic bonds could be measured and evaluated. At least it will be concluded with an outlook for the feasibility of eutectic bonding in 3-d integrated smart micro systems.