On-chip circuit for massively parallel BTI characterization

This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be tested in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the tested devices have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out on the new 28nm node IMEC technology.