Investigation of candidate VRM topologies for future microprocessors [voltage regulator modules]

Author

Zhou, Xunwei ; Zhang, Xingzhu ; Liu, Jiangang ; Wong, Pit-Leong ; Jiabin Chen ; Wu, Ho-Pu ; Amoroso, Luca ; Lee, Fred C. ; Chen, Jiabin

Author_Institution

Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

Volume

1

fYear

1998

fDate

15-19 Feb 1998

Firstpage

145

Abstract

Future generation microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Today´s voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. In this paper, a candidate topology, interleaved quasi-square wave, is proposed. Its design, simulation and experimental results are presented

Keywords

DC-DC power convertors; computer power supplies; microprocessor chips; power MOSFET; power semiconductor switches; switching circuits; voltage regulators; VRM topologies; decoupling capacitors; design; experiments; interleaved quasi-square wave topology; microprocessor power supplies; output filter capacitors; simulation; transient slew rates; voltage regulator modules; Capacitors; Circuit topology; Energy management; Filters; Microprocessors; Power supplies; Power system transients; Rectifiers; Regulators; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 1998. APEC '98. Conference Proceedings 1998., Thirteenth Annual

Conference_Location

Anaheim, CA

Print_ISBN

0-7803-4340-9

Type

conf

DOI

10.1109/APEC.1998.647683

Filename

647683