Using carbon nanotube in digital memories

With the continuous technology scaling, interconnect delay plays an increasingly important role in determining integrated circuit performance. This has motivated tremendous research efforts on searching better interconnect technologies as alternatives to conventional Cu wires, among which carbon nanotube (CNT) has received the most attentions. However, in spite of its well demonstrated relatively small delay over long distance, CNT has several drawbacks that prevent it from being used in practice, including fabrication difficulty and contact resistance. This work concerns the practical use of carbon nanotube in digital memories, in particular this paper presents a simple yet effective hybrid word-line/bit-line design solution that aims to complement metal wire with CNT in order to well leverage the low resistance property of CNT and meanwhile embrace the drawbacks inherent in CNT. HSPICE simulations were carried out to demonstrate the effectiveness of this hybrid design strategy at technology nodes down to 16 nm.