DocumentCode
3198553
Title
On combining technology and theory in search of a parallel computation model
Author
JáJá, Joseph
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
fYear
1996
fDate
35289
Firstpage
115
Lastpage
123
Abstract
A fundamental problem in parallel computing is to design high-level, architecture independent, algorithms that execute efficiently on general purpose parallel machines. The aim is to be able to achieve portability and high performance simultaneously. A key to accomplishing this is the existence of a computation model that can bridge the gap between the high level programming models and the underlying hardware models. There are currently two factors that make this fundamental problem more tractable. The first is the emergence of a dominant parallel architecture consisting of a number of powerful microprocessors interconnected by either a proprietary interconnect, or a standard off-the-shelf interconnect (such as an ATM switch). The second factor is the emergence of standards, such as the message passing standard MPI, for which efficient implementations are either available or about to appear on most machines. Our recent work has exploited these two developments by developing a methodology based on (1) a simple computation model for the current MIMD platforms that incorporates communication cost into the complexity of the algorithms, and (2) a SPMD programming model that makes effective use of communication primitives. We describe our approach for validating the computation model based on extensive experimentation and the development of benchmarks, and discuss its extension to the emerging clusters of Symmetric Multiprocessors (SMPs) architecture
Keywords
parallel algorithms; parallel architectures; parallel machines; MIMD platforms; Symmetric Multiprocessors; general purpose parallel machines; high performance; parallel computation model; parallel computing; portability; Parallel algorithms; Parallel architectures; Parallel machines;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 1996. Proceedings of the 1996 ICPP Workshop on Challenges for
Conference_Location
Ithaca, NY
ISSN
1530-2016
Print_ISBN
0-8186-7623-X
Type
conf
DOI
10.1109/ICPPW.1996.538597
Filename
538597
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