Integrated Reliability Workshop

The IEEE International Integrated Reliability Workshop (IRW) originated from the Wafer Level Reliability Workshop in 1982. The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, paper presentations, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and future semiconductor applications as well as ample opportunity for discussions and interactions with colleagues. IIRW 2012 will include a special resistive memory invited session. Resistive memory abstract submissions are also encouraged. Additional hot reliability topics for the workshop include: high-K and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III–V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, and single event upsets. We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: • Designing-in reliability (products, circuits, systems, processes) • Resistive Memory: Degradation Mechanisms • Deep sub-micron transistor and circuit reliability • Customer product reliability requirements / manufacturer reliability tasks • Root cause defects, physical mechanisms, and simulations • Wafer level reliability tests, test approaches, and reliability test structures