Implementation of chip embedding processes for the creation of miniaturized system-in-packages

This paper details the newest developments in chip embedding technologies for chips with a pitch of 100μm. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400μm pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100μm pitch. All Embedded chip-QFN packages have been manufactured in 10"×14" panels at prototype level. This paper also presents developments in semi-additive processing up to 15μm L/S copper structuring on very thin copper foils. Package reliability studies have shown excellent resin/chip adhesion and good thermo-mechanical stability of embedded interfaces for all tests.