TSV modeling and noise coupling in 3D IC

Through silicon via (TSV) is a promising vertical interconnection method to achieve a 3-dimensional integrated circuit (3D IC) system. However, TSV noise coupling becomes one of the most significant considerations due to the fine pitch integration with TSVs for the smaller form factor. Thus, electrical model of TSV is proposed which is valid up to 20GHz. With the proposed model of TSV, noise coupling model between TSVs is also presented by using 3D TLM method. As for the noise isolation methods between TSVs, p+ and deep n-well guard ring structure are proposed for the substrate noise coupling suppression. In addition, the effect of those proposed shielding techniques is studied in the frequency and time domain.