DocumentCode :
3199665
Title :
Soft Error Rate Determination for Nanometer CMOS VLSI Logic
Author :
Wang, Fan ; Agrawal, Vishwani D.
Author_Institution :
Auburn Univ., Auburn
fYear :
2008
fDate :
16-18 March 2008
Firstpage :
324
Lastpage :
328
Abstract :
Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation and charged particles. These phenomena, also known as single-event upset (SEU) induce current pulses at random times and random locations in a digital circuit. In this paper we model neutron-induced soft errors using two parameters, namely, frequency and intensity. Our soft error rate (SER) estimation method propagates both frequency (expressed as probability) and intensity as the width of single event transient (SET) pulses expressed as probability density functions through the circuit. With this model we are able to accurately model electrical masking factors in logic circuits. Also, the error pulse width density information at primary outputs of the logic circuit allows evaluation of SER reduction schemes such as time or space redundancy.
Keywords :
CMOS integrated circuits; VLSI; logic circuits; masks; electrical masking; logic circuits; nanometer CMOS VLSI circuits; nanometer CMOS VLSI logic; single event transient; single event upset; soft error rate determination; CMOS logic circuits; Digital circuits; Error analysis; Frequency estimation; Logic circuits; Pulse circuits; Semiconductor device modeling; Single event upset; Space vector pulse width modulation; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 2008. SSST 2008. 40th Southeastern Symposium on
Conference_Location :
New Orleans, LA
ISSN :
0094-2898
Print_ISBN :
978-1-4244-1806-0
Electronic_ISBN :
0094-2898
Type :
conf
DOI :
10.1109/SSST.2008.4480247
Filename :
4480247
Link To Document :
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