Investigation into the impact of component floor plan layout on the overall reliability of electronics systems in harsh environments

For many harsh environment, high reliability product applications such as automotive, military and avionics, the solder joint fatigue behaviour of electronic packages subjected to accelerated thermal cycling is frequently used as an estimate of `in field´ reliability. Although the fatigue response of the individual package interconnect styles is understood in terms of material sets used and CTE differences between component and board, the influence of component location on the Printed Circuit Board (PCB) floor plan or PCB constraint points has not previously been investigated. This paper outlines preliminary investigatory work undertaken using Finite Element Modelling (FEM) to study such influences on the performance and behaviour of solder joints.