DocumentCode
3199899
Title
Design of IP Media Accelerator
Author
Qing Wang ; Wenbo Shen ; Yu Li ; Zhenbo Zhu
Author_Institution
IBM, Beijing
fYear
2007
fDate
2-5 July 2007
Firstpage
1195
Lastpage
1198
Abstract
Multimedia processing is computation intensive and not efficient to be proceeded on current GPP (general purpose processor) based server architectures. In order to enhance the multimedia processing capability of servers, we propose a re-configurable multi-core platform for media and network acceleration. The platform is composed of DSP array and FP-GAs, and is compatible to IBM blade server specification. In this paper, we highlight the design challenge and present the hardware and software design of this accelerator. The prototype of IP Media Server (IMS) is implemented on this platform, which completes the essential functions of voice conference application. The first-stage test results are presented and the perspective of future work is proposed.
Keywords
digital signal processing chips; field programmable gate arrays; multimedia servers; DSP array; FPGAs; IBM blade server; IP media accelerator; IP media server; general purpose processor; hardware design; media acceleration; multimedia processing; network acceleration; reconfigurable multicore platform; server architectures; software design; Acceleration; Application software; Blades; Computer architecture; Digital signal processing; Hardware; Network servers; Prototypes; Software design; Software prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo, 2007 IEEE International Conference on
Conference_Location
Beijing
Print_ISBN
1-4244-1016-9
Type
conf
DOI
10.1109/ICME.2007.4284870
Filename
4284870
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