Title :
From interpreted Petri net specification to reprogrammable logic controller design
Author :
Adamski, Marian ; Monteiro, Joao L.
Author_Institution :
Inst. of Comput. Eng. & Electron., Tech. Univ. of Zielona Gora, Poland
Abstract :
The goal of this paper is to present the design methodology for the modelling and synthesis of discrete event controllers for compact, fast and reliable embedded systems, using related Petri net theory, rule-based system theory (conditional mathematical logic), and hardware description languages (VHDL, Verilog). The well structured specification, which is represented in the human readable logic language, has a direct impact on the validation, formal verification and implementation of application specific logic controllers (ASLC) mapped into reconfigurable logic devices (FPGA). Reprogrammable logic controllers (RLC) may replace traditional PLCs in many industrial applications
Keywords :
Petri nets; control system synthesis; discrete event systems; field programmable gate arrays; formal verification; hardware description languages; programmable controllers; FPGA; Petri net specification; Petri net theory; VHDL; Verilog; application specific logic controllers; conditional mathematical logic; discrete event controllers synthesis; fast embedded systems; formal verification; hardware description languages; human readable logic language; industrial applications; reconfigurable logic devices; reliable embedded systems; reprogrammable logic controller design; rule-based system theory; Control system synthesis; Design methodology; Embedded system; Hardware design languages; Knowledge based systems; Logic design; Logic devices; Mathematical model; Reconfigurable logic; Reliability theory;
Conference_Titel :
Industrial Electronics, 2000. ISIE 2000. Proceedings of the 2000 IEEE International Symposium on
Conference_Location :
Cholula, Puebla
Print_ISBN :
0-7803-6606-9
DOI :
10.1109/ISIE.2000.930478
