An RSA processor for near real-time operation

The goal of this paper is to research the feasibility of designing and implementing an economical architecture for the real time computation of RSA algorithm, in a sense that the architecture could be implemented on single ASIC with standard logic and power supply. The main challenge in implementing such a design comes out of a need to make arithmetic computations involving very large numbers with bit lengths of thousands of digits. To overcome this, special design of hardware is needed at the algorithms level, and also at the circuit level. The final implementation of our hardware is based on four known algorithms leveraging the use of a CCSA (Carry-Completion-Sensing-Adder) as the building block of the design. This implementation makes it convenient to benefit from a fast hardware adder in a simple algorithm choice, while attempting to keep hardware costs down. The results support the initial assumption that it is possible to implement an embedded RSA encryption engine for real-time or near real-time operation by exploiting the features of a custom hardware processor.