DocumentCode
320062
Title
Mapping nested loops onto distributed memory multiprocessors
Author
Koziris, Nectarios ; Papakonstantinou, George ; Tsanakas, Panayotis
Author_Institution
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece
fYear
1997
fDate
10-13 Dec 1997
Firstpage
35
Lastpage
41
Abstract
The paper presents Chain grouping; a new low complexity method for the problem of partitioning the index space into groups with little intercommunication requirements, for mapping onto distributed mesh connected architectures. First the loop iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the index space is divided into discrete groups of related computations, which are assigned to different processors, while preserving the optimal makespan. The Chain grouping method is based on grouping along a uniform chain of computations, formed by a particular dependence vector. This vector will be proved as the best to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved, and the references to intragroup computations are considerably increased. The partitioned groups are afterwards assigned to meshes of processors. The resulting space mapping maximises processor utilisation and cuts down overall communication delays while preserving the optimal hyperplane time schedule
Keywords
distributed memory systems; parallel architectures; processor scheduling; Chain grouping; communication delays; dependence vector; discrete groups; distributed memory multiprocessors; distributed mesh connected architectures; hyperplane method; index space partitioning; intercommunication requirements; intragroup computations; loop iterations; low complexity method; minimum time displacement; nested loops; optimal hyperplane scheduling; optimal hyperplane time schedule; optimal makespan; partitioned groups; processor utilisation; space mapping; uniform chain; Computer architecture; Computer science; Concurrent computing; Delay effects; Parallel architectures; Parallel processing; Processor scheduling; Scheduling algorithm; Systolic arrays; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on
Conference_Location
Seoul
Print_ISBN
0-8186-8227-2
Type
conf
DOI
10.1109/ICPADS.1997.652527
Filename
652527
Link To Document