DocumentCode
3202901
Title
CCHIME: a cache coherent hybrid interconnected memory extension
Author
Farrens, Matthew ; Park, Arvin ; Woodruff, Allison
Author_Institution
Div. of Comput. Sci., California Univ., Davis, CA, USA
fYear
1992
fDate
23-26 Mar 1992
Firstpage
573
Lastpage
577
Abstract
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent caches. The authors achieve this by replacing the memory modules and final stages of a multistage interconnection network with clusters of coherent caches. The performance of Cache Coherent Hybrid Interconnected Memory Extension (CCHIME) is evaluated by analyzing the results of extensive simulations of the network and coherent cache clusters. These results indicate that the CCHIME architecture can achieve lower memory access latencies and higher throughputs than typical multistage interconnection networks
Keywords
buffer storage; multiprocessor interconnection networks; shared memory systems; CCHIME; cache coherent hybrid interconnected memory extension; coherent caches; contention reduction; hybrid shared memory architecture; memory access latencies; multistage interconnection network; scalability; simulations; throughputs; Computational modeling; Computer science; Delay; Memory architecture; Multiprocessor interconnection networks; Performance analysis; Scalability; Switches; Telecommunication traffic; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1992. Proceedings., Sixth International
Conference_Location
Beverly Hills, CA
Print_ISBN
0-8186-2672-0
Type
conf
DOI
10.1109/IPPS.1992.222965
Filename
222965
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