Some architectural and compilation issues in the design of hierarchical shared memory multiprocessors

Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The authors discuss architectures based on hierarchical memories which exploit the notion of partial sharing of variables to significantly reduce latency and synchronization overheads. They examine a particular class of architectures, the tree-structured hierarchical memory multiprocessor architectures (THMM), by suggesting an implementation and considering the compile-time parallelization of nonnested iterative loops with constant dependence distance and unit stride. They compare speedup figures for parallelized loops on the THMM and on a conventional memory multiprocessor