A word-line boost driver design for low operating voltage 6T-SRAMs

Author

Shakir, Tahseen ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of WaterlooWaterloo, Waterloo, ON, Canada

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

33

Lastpage

36

Abstract

Low voltage operated embedded SRAMs in nanometric CMOS technologies are sensitive to PVT variations and hence can cause poor yield. In this paper, we exploit the concept of Dynamic Noise Margin (DNM) to enhance the 6TSRAM cell design flexibility and reliability. In particular, a transition Word-line driver (WL) boost circuit design is proposed. Carried-out post layout Monte Carlo simulations on a 400 mV, 4 Kbit 6T SRAM sub array in TSMC 65nm CMOS technology show the benefit of proposed scheme. A 28.5% improvement in the developed bitline differential voltage and a 39% reduction in cell leakage current are achieved.

Keywords

CMOS memory circuits; Monte Carlo methods; SRAM chips; circuit reliability; network synthesis; 6T-SRAM; DNM; Monte Carlo simulations; PVT variations; TSMC; boost circuit design; dynamic noise margin; low operating voltage; nanometric CMOS technologies; reliability; transition word-line driver; word-line boost driver design; Arrays; CMOS integrated circuits; Leakage current; Microprocessors; Random access memory; Transistors; SRAM reliability; Word-line boost; Yield; dynamic noise margin; low leakage; low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6291950

Filename

6291950