Evaluation of circuit styles and VLSI logic designs of pentacene OTFTs

Organic electronics have immense potential over a wide spectrum of applications. In the present scenario, an abundance of investigations are being followed on the transistor operation and its characterization. However, circuit level research focus is not that common. Therefore, we sensed the urgency to provide a complete assessment of the different circuit styles, which are, the diode-load, zero-V_gs, pseudo-E and pseudo-D, in ratioless and ratioed logic. A comparative evaluation of the collective circuit behavior of each design style is critical. The major parameters, such as, power consumption, noise margin of high and low level signal, circuit speed, on current and output voltage swing were measured and thereupon, analyzed to decide upon the optimum circuit style for cascading. The inverter, NAND and NOR logic gates, and a 5-inverter ring oscillator were further analyzed, using the pentacene OTFT model file, to realize the best architecture for integration in large scale circuits. Based on our evaluations, the lowest power consumption was in case of the zero-V_gs and pseudo-D design style, along with, a fast circuit operation speed. The pseudo-D circuit configuration, not only provides the maximum V_out swing, but it has the best performance.