VHDL-based design of FSM with concurrent error detection capability

This paper presents a VHDL-based methodology to design Self-Checking (SC) Finite State Machines (FSM). The methodology provides a library of pre-designed, parameterized concurrent error-detection (CED) modules as well as a VHDL code template that allow easily creation of synthesizable highlevel description of the SC FSM with minor additional design development time. The template offers selection of error-detecting schemes that will be used for encoding output data and states of the FSM. The generated SC FSM description can be simulated and synthesized with commercial tools. Effectiveness of the methodology is evaluated on a set of benchmark FSMs.