Evaluation of fault tolerant channel buffers for improving reliability in NoCs

Elastic or channel buffers can improve the overall power and area overhead of Network-on-Chip (NoC) architectures by reducing or replacing large, power hungry router buffers. In this paper, we design three fault tolerant schemes for our channel buffers which are used in a concentrated torus (CTorus) topology to reduce power consumption and improve throughput and latency. Our proposed fault tolerant techniques on CTorus topology are evaluated using the Synopsys Design Compiler and our results show (i) an improvement in energy-delay product (EDP) ranging from 20% to 43%, (ii) improvement in saturation throughput of 32% and (iii) an overall reduction in area overhead by 53-68% over other state-of-the-art electrical topologies.