DocumentCode :
3203842
Title :
Performance enhancement defect tolerance in the cell matrix architecture
Author :
Saha, C.R. ; Bellis, S.J. ; Mathewson, A. ; Popovici, E.M.
Author_Institution :
Nat. Microelectron. Res. Centre, Cork, Ireland
Volume :
2
fYear :
2004
fDate :
16-19 May 2004
Firstpage :
777
Abstract :
This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture, In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field programmable gate arrays using their Supercell approach, is studied. Architectural constraints to implement fault tolerant circuit design in this architecture are discussed. Some modifications of its basic Structure, such as the integration of circuitry for error correction and scan path, to enhance fault tolerant circuits design are introduced and are compared to the Supercell approach.
Keywords :
CMOS digital integrated circuits; error correction; fault tolerance; integrated circuit design; Cell Matrix; Supercell approach; architectural constraints; cell matrix architecture; error correction; fault tolerant circuit implementation; fault tolerant circuits design; field programmable type architecture; performance enhancement defect tolerance; scan path; Circuit faults; Circuit synthesis; Circuit testing; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Microelectronics; Redundancy; Table lookup; Telecommunication computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2004. 24th International Conference on
Print_ISBN :
0-7803-8166-1
Type :
conf
DOI :
10.1109/ICMEL.2004.1314949
Filename :
1314949
Link To Document :
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