Implementation of Color Filtering on FPGA

The objective of this paper is to construct a real time hardware image processing system on field programmable gate array (FPGA). The chosen image processing algorithm is a single color filtering algorithm. This work utilizes Altera DE2 development board empowered by the Cyclone II FPGA paired with a 1.3 mega pixel CMOS camera from Terasik Technologies. Verilog HDL is chosen as the hardware programming language for this system and its compiled using Quartus II program. The functionality of the algorithm is first verified in Matlab, simulating the expected output of the system before implementing it onto the FPGA development board. Two band-pass-filter-like algorithms has been tested and implemented. The first is the single band-pass filter with threshold selected according to the International Commission on Illumination (CIE) values. The second is the double band-pass-filter algorithm. Work is currently conducted to quantify the effectiveness of the band-pass filtering algorithm on FPGA before proceeding to test and implement the triple and quadruple band-pass filtering methods.