Title :
VLSI implementation of a 256×256 crossbar interconnection network
Author :
Choi, Kyusun ; Adams, William S.
Author_Institution :
Eng. Comput. Lab., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. The paper presents the analysis of VLSI layout size and signal delay of the previous crossbar circuits. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256×256 crossbar on a 1cm2 CMOS VLSI chip
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; multiprocessor interconnection networks; 256×256 crossbar; CMOS VLSI chip; VLSI layout size; crossbar interconnection network; parallel processing systems; signal delay; Application software; Circuits; Concurrent computing; Decoding; Delay; Multiplexing; Multiprocessor interconnection networks; Signal analysis; Switches; Very large scale integration;
Conference_Titel :
Parallel Processing Symposium, 1992. Proceedings., Sixth International
Conference_Location :
Beverly Hills, CA
Print_ISBN :
0-8186-2672-0
DOI :
10.1109/IPPS.1992.223031
