A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC

A single-channel 1.0-GS/s 8-bit Voltage-Buffer-Free Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the chip area grandly. An improved single-diode switch with an extra reset path is proposed as inter-stage sampling switches. The ADC implemented in 65nm CMOS technology achieves SNDR of 47.5 dB and SFDR of 57.8 dB for 487.3 MHz input frequency at the rate of 1.0-GS/s. The power consumption is 75 mW with supply voltage of 1.2 V.