Title :
Vector Hartley transform employing multiprocessors
Author :
Mahapatra, Rabi N. ; Kumar, Akhilesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
Many parallel implementations for signal processing transforms have already been reported. The implementation of Hou´s FHT algorithm (1987) has been studied on three multiprocessor architectures (MPAs): multiprocessors connected through a shared bus; multiprocessors connected by an indirect binary n-cube multistage interconnection network and mesh connected multiprocessors. The article analyzes the performance of a vector Hartley transform algorithm on these MPAs
Keywords :
multiprocessor interconnection networks; parallel algorithms; performance evaluation; transforms; FHT algorithm; Hou; indirect binary n-cube; mesh connected multiprocessors; multiprocessor architectures; multistage interconnection network; performance analysis; shared bus; signal processing transforms; vector Hartley transform algorithm; Content addressable storage; Discrete Fourier transforms; Discrete transforms; Fast Fourier transforms; Fourier transforms; Information retrieval; Kernel; Memory; Performance analysis; Signal processing algorithms;
Conference_Titel :
Parallel Processing Symposium, 1992. Proceedings., Sixth International
Conference_Location :
Beverly Hills, CA
Print_ISBN :
0-8186-2672-0
DOI :
10.1109/IPPS.1992.223038
