DocumentCode :
3204471
Title :
Analysis on the column sum boundaries of decimal array multipliers
Author :
Bozdas, Kenan ; Alkar, Ali Ziya
Author_Institution :
Dept. of Electr. & Electron. Eng., Hacettepe Univ., Ankara, Turkey
fYear :
2012
fDate :
5-8 Aug. 2012
Firstpage :
318
Lastpage :
321
Abstract :
The hardware implementations of decimal arithmetic operations, which are commonly used in financial, scientific, and internet-based applications requiring accuracy and speed, become prominent. In this paper we first analyze the column sum boundaries of n-digit parallel decimal array multipliers (PDAM). A general form of the problem is formed and a heuristic solution is found with Genetic Algorithm (GA) for 16-digit multiplication. Then, for small n-digit multipliers the GA results are proved with exhaustive search. Finally, new tight boundaries on the column sums are used in a hardware implementation of a 16-digit PDAM. Inclusion of the proposed boundaries provides an 8% speedup or 20% less area.
Keywords :
genetic algorithms; multiplying circuits; 16-digit PDAM; 16-digit parallel decimal array multiplier; GA; column sum boundary analysis; decimal arithmetic operation; financial application; genetic algorithm; hardware implementation; heuristic solution; internet-based applications; scientific application; Arrays; Computers; Delay; Equations; Genetic algorithms; Hardware; Mathematical model;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location :
Boise, ID
ISSN :
1548-3746
Print_ISBN :
978-1-4673-2526-4
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2012.6292021
Filename :
6292021
Link To Document :
بازگشت