• DocumentCode
    3204481
  • Title

    Memory requirements to balance thus asymptotically full-speedup FFT computation on processor arrays

  • Author

    Shieh, Jiann-Cherng

  • Author_Institution
    Aero Ind. Dev. Center, Taichung, Taiwan
  • fYear
    1992
  • fDate
    23-26 Mar 1992
  • Firstpage
    208
  • Lastpage
    210
  • Abstract
    The paper proves that for a linearly-connected array of α processors or a mesh-connected array of α2 processors, where each processor has computation bandwidth C, I/O bandwidth I and C/I=logm, Ω(mα) memory size is required in each processor to minimize the I/O requirement in balancing the FFT computation. Then it presents balanced FFT algorithms on these arrays to meet their memory size lower bounds. These algorithms are time optimal exhibiting full speedups
  • Keywords
    computational complexity; fast Fourier transforms; multiprocessor interconnection networks; parallel algorithms; I/O bandwidth; balanced FFT algorithms; computation bandwidth; linearly-connected array; memory size lower bounds; mesh-connected array; processor arrays; time optimal algorithms; Bandwidth; Computer industry; Concurrent computing; FETs; Hardware; Processor scheduling; Sorting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1992. Proceedings., Sixth International
  • Conference_Location
    Beverly Hills, CA
  • Print_ISBN
    0-8186-2672-0
  • Type

    conf

  • DOI
    10.1109/IPPS.1992.223045
  • Filename
    223045
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3204481