Jitter analysis for DS-3 to SONET interface circuit with reduced complexity

The feasibility is discussed of designing a DS-3 to 28 VT 1.5 synchronous optical network (SONET) interface circuit without using intermediate DS-2 and DS-1 desynchronizer phase-lock loops (PLLs). Elimination of intermediate PLLs results in a significant reduction in the cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy. The primary concern of implementing such an interface is the effect on accumulated DS-1 waiting time jitter. In order to analyze jitter accumulation, two multiplex models are used. Both models consist of back-to-back M13 multiplexing followed by back-to-back DS-1 to VT 1.5 mapping. The first model includes intermediate DS-2 and DS-1 desynchronizer PLLs, while the second model does not. The jitter analysis and results for both models are given. It is estimated that elimination of these PLLs can reduce the circuit complexity by 14000 gates in a DS-3 to 28 VT1.5 interface design.<>