DocumentCode
3204701
Title
The bus-usage method for the analysis of reconfiguring networks algorithms
Author
Ben-Asher, Yosi ; Schuster, Assaf
Author_Institution
Dept. of Math. & Comput. Sci., Haifa Univ., Israel
fYear
1992
fDate
23-26 Mar 1992
Firstpage
146
Lastpage
149
Abstract
Reconfigurable networks have attracted increased attention recently, as an extremely strong parallel model which is realizable in hardware. The authors consider the basic problem of gathering information which is dispersed among the nodes of the network. They analyze the complexity of the problem on reconfigurable linear-arrays. The analysis introduces a novel criteria for the efficiency of reconfigurable network algorithms, namely the bus-usage. The bus-usage quantity measures the utilization of the network sub-buses by the algorithm. It is shown how this yields bounds on the algorithm run-time, by deriving a run-time to bus-usage trade-off
Keywords
multiprocessor interconnection networks; parallel algorithms; bus-usage method; complexity analysis; network sub-buses; reconfigurable linear-arrays; reconfigurable network algorithms; Algorithm design and analysis; Assembly; Computer science; Concurrent computing; Hardware; Mathematical model; Mathematics; Parallel machines; Runtime; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1992. Proceedings., Sixth International
Conference_Location
Beverly Hills, CA
Print_ISBN
0-8186-2672-0
Type
conf
DOI
10.1109/IPPS.1992.223056
Filename
223056
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