A digitally assisted, pseudo-resistor-less amplifier in 65nm CMOS for neural recording applications

A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large `pseudo-resistors´ needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier.