• DocumentCode
    3204790
  • Title

    Routing BPC permutations in VLSI

  • Author

    Alnuweiri, Hussein M.

  • Author_Institution
    Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
  • fYear
    1992
  • fDate
    23-26 Mar 1992
  • Firstpage
    116
  • Lastpage
    119
  • Abstract
    A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. The paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/ Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1⩽Q ⩽√N/w
  • Keywords
    VLSI; logic design; multiprocessor interconnection networks; parallel processing; BPC permutations; VLSI; VLSI designs; interconnection networks; permutations; Delay effects; Design methodology; Digital arithmetic; Integrated circuit interconnections; Intelligent networks; Parallel processing; Pins; Propagation delay; Routing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1992. Proceedings., Sixth International
  • Conference_Location
    Beverly Hills, CA
  • Print_ISBN
    0-8186-2672-0
  • Type

    conf

  • DOI
    10.1109/IPPS.1992.223061
  • Filename
    223061
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3204790