DocumentCode
3204862
Title
CMOS implementation comparison of NCL gates
Author
Parsan, Farhad A. ; Smith, Scott C.
Author_Institution
Dept. of Electr. Eng., Univ. of Arkansas, Fayetteville, AR, USA
fYear
2012
fDate
5-8 Aug. 2012
Firstpage
394
Lastpage
397
Abstract
Various CMOS implementations of asynchronous NULL Convention Logic (NCL) gates have been compared in terms of area, speed, energy, power, supply voltage, and noise. Additionally, a new approach to design semi-static NCL gates has been introduced. Each gate type is used to realize a delay-insensitive 4×4 NCL multiplier and the simulation results are compared. It is shown that different realizations excel in different design parameters. This paper aims to provide NCL designers with the tradeoffs of using various NCL gate types.
Keywords
CMOS logic circuits; integrated circuit design; logic design; logic gates; CMOS implementation; NCL gate types; asynchronous NULL convention logic gates; delay-insensitive NCL multiplier; design parameters; semistatic NCL gates design; CMOS integrated circuits; Delay; Inverters; Logic gates; Noise; Standards; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location
Boise, ID
ISSN
1548-3746
Print_ISBN
978-1-4673-2526-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2012.6292040
Filename
6292040
Link To Document