Efficient algorithm and hardware implementation of 3N for arithmetic and for Radix-8 encodings

The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance than the use of the conventional RCA. The proposed CLA-like 64-bit encoder achieves 1.73 ns which is approximately 20% faster than the use of the conventional CLA.