Title :
Sessions: VLSI design for error-correcting codes
Abstract :
The following topics are dealt with: Viterbi decoding VLSI design and performance; trellis partitioning; variable-rate sequential decoding; data broadcast decoding; Reed-Solomon code systolic arrays and chips.<>
Keywords :
VLSI; cellular arrays; decoding; digital signal processing chips; error correction codes; integrated memory circuits; memory architecture; sequential circuits; state assignment; Reed-Solomon code systolic arrays; VLSI design; Viterbi decoding; data broadcast decoding; error-correcting codes; trellis partitioning; variable-rate sequential decoding; Circuits; Convolutional codes; Decoding; Error correction codes; Forward error correction; Hardware; Large scale integration; Random access memory; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Information Theory, 1988. Abstracts of Papers., 1988 IEEE International Symposium on
Conference_Location :
Kobe, Japan
DOI :
10.1109/ISIT.1988.22307
