A superscalar processor for a medium-grain reconfigurable hardware

In this paper a novel modular superscalar execution core is presented for a medium grain reconfigurable hardware. The processor can be configured for varying path widths, reservation station depths, and reorder buffer sizes with minimal redesign effort. An analysis comparing the superscalar core with a five-stage execution core shows that a speedup of 2.073 can easily be achieved while increasing area by only 29%.