DocumentCode
3205183
Title
FinFET 3T and 3T1D dynamic RAM cells
Author
Gerik, Colby M. ; Turi, Michael A. ; Delgado-Frias, José G.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fYear
2012
fDate
5-8 Aug. 2012
Firstpage
454
Lastpage
457
Abstract
In this study we present 3T and 3T1D DRAM cells designed using FinFET technology. Overall, the 3T DRAM cell has a 43.6% faster write speed than the 3T1D cell and uses less dynamic current (30.4% less write current and 14.6% less read current). The FinFET 3T1D DRAM cell offers a 16.7% faster read speed and 48.6% less read leakage current than the 3T1D cell. The 3T DRAM cell offers less variation in delays, up to 37% less than the 3T1D cell for write delay, due to parameter corner simulations. Overall for a system, the 3T FinFET DRAM cell is more promising due to its low dynamic current and significantly shorter write speed which leads to a smaller maximum delay.
Keywords
DRAM chips; MOSFET; FinFET DRAM cell; FinFET technology; dynamic RAM cell; write speed; CMOS integrated circuits; Capacitance; Delay; FinFETs; Logic gates; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location
Boise, ID
ISSN
1548-3746
Print_ISBN
978-1-4673-2526-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2012.6292055
Filename
6292055
Link To Document